1. Field of the Invention
The embodiments of the invention generally relate to multi-fin field effect transistors and, more particularly, to multi-fin field effect transistors having source/drain fin straps configured to minimize capacitance to the gate.
2. Description of the Related Art
As transistor design is improved and evolves, the number of different types of transistors continues to increase. Multi-gated non-planar metal oxide semiconductor field effect transistors (FETs), including dual-gate non-planar FETs (e.g., finFETs) and tri-gate non-planar FETs, were developed to provide scaled devices with faster drive currents and reduced short channel effects over planar FETs.
Dual-gate non-planar FETs are FETs in which a channel region is formed in the center of a thin semiconductor fin. The source and drain regions are formed in the opposing ends of the fin on either side of the channel region. Gates are formed on each side of the thin semiconductor fin, and in some cases, on the top or bottom of the fin as well, in an area corresponding to the channel region. FinFETs specifically are dual-gate non-planar FETs in which the fin is so thin as to be fully depleted. The effective fin width is determined by the fin height (e.g., short wide fins can cause partial depletion of a channel). For a finfet, a fin thickness of approximately one-fourth the length of the gate (or less) can ensure suppression of deleterious short-channel effects, such as variability in threshold voltage and excessive drain leakage currents. FinFETs are discussed at length in U.S. Pat. No. 6,413,802 to Hu et al., which is incorporated herein by reference
Tri-gate non-planar FETs have a similar structure to that of dual-gate non-planar FETs; however, the fin width and height are approximately the same so that gates can be formed on three sides of the channel, including the top surface and the opposing sidewalls. The height to width ratio is generally in the range of 3:2 to 2:3 so that the channel will remain fully depleted and the three-dimensional field effects of a tri-gate FET will give greater drive current and improved short-channel characteristics over a planar transistor. For a detail discussion of the structural differences between dual-gate and tri-gate FETs see “Dual-gate (finFET) and Tri-Gate MOSFETs: Simulation and Design” by A Breed and K. P. Roenker, Semiconductor Device Research Symposium, 2003, pages 150-151, December 2003 (incorporated herein by reference).
The effective channel width of both dual-gate and tri-gate FETs can be increased by incorporating multiple fins into the FET structure. In such multi-fin FETs, the source/drain regions of each fin are often strapped together with conductive straps. These source/drain straps mimic the source/drain regions of planar field effect transistors and allow for more flexible placement of contact vias. However, capacitance between the gate and the source/drain straps and, particularly, between the gate and a drain strap can significantly increase circuit delay (i.e., degrade switching speed) and increase power, due to the Miller effect. Therefore, there is a need in the art for a multi-fin field effect transistor structure and method of forming the structure that provides low resistance strapping of the source/drain regions of the fins, while also maintaining low capacitance to the gate.